In a communications network, a network adapter manages the transmission and reception of data packets by transferring data between the network and a shared memory in a computer system. The shared memory is used by several different devices including the system CPU, I/O devices and disks as well as the network. The network adapter accesses the shared memory by a shared system bus.
The shared memory has buffers in which data packets are stored. The buffers are accessed through buffer descriptors. Buffer descriptors define specific information about the buffers and the data packets stored in the buffers, e.g. location, data type, length, and size. The buffer descriptors are located in the shared memory along with the data packets. To transmit or receive a data packet, the network adapter must open a buffer descriptor, transfer the data packet to or from a buffer and then close the buffer descriptor. A buffer descriptor is opened by moving it out of the system memory to a memory in the network adapter. A buffer descriptor is closed by moving it back into the shared memory from the memory in the network adapter. Each descriptor and data transfer operation consists of a system bus request-grant phase and a data bus cycle in which a buffer descriptor or a data packet is transferred. The time elapsed during the request-grant phase is called latency. Even on a high speed system, latency can be high, typically several microseconds, while the data bus cycle is fast, typically a number of nanoseconds. The speed of transmitting or receiving data packets is limited by latency. The latency in opening and closing buffer descriptors is a large component in the delays in packet reception and transmission.
In a cut-through network adapter, a data packet is copied through the adapter into the shared memory. In order to accomplish the data transfer, the adapter buffers the data packet in a first-in, first-out queue (FIFO) on a network controller chip in the adapter. A typical FIFO may, for example, be 128-1024 bytes while data packets may be as large as 4500 bytes. Therefore, typically only small data packets may reside in entirety in the FIFO. Larger data packets need to be transferred through. Controlling access to the system bus in order to access buffer descriptors is key to data transfer. In order to transfer data, the adapter needs to know where to put the data in the system memory, that is, the adapter needs to access buffer descriptors in order to know if a particular location is available.
FIFO size is dependent on system bus latency. The larger the delay from request to grant, the larger the FIFO needs to be in order to transfer data through the network adapter without losing data packets. A larger FIFO would increase the efficiency of data transfer but it would also require a larger, more expensive network controller chip which would need more power.
It remains desirable to transfer large data packets through a network adapter more efficiently, without increasing the size of the network controller chip.